Requirements exist during the testing of certain circuits, such as static random access memory circuits, and also dynamic random access memory circuits, to enable special test modes of the circuits not only during manufacturing but also by a customer at the module or package level. These tests may include, but are not limited to, voltage acceleration tests on parts with on-chip supply regulators, self-test initiation and fuse blown signatures. Use of special pins connected to these circuits for testing purposes is not feasible in many instances due to the lack of any extra pin locations or positions on industry standard packages.
In U.S. Pat. No. 4,612,499, filed Nov. 7, 1983, there is disclosed a test input circuit which uses specially designed complementary metal oxide semiconductor (CMOS) transistors controlled by a middle range voltage signal connected to an input pin used for data input in normal operation.
U.S. Pat. No. 4,334,307, filed Dec. 28, 1979, discloses a system using firmware for executing a self-test routine each time the system goes through a power-up cycle.
U.S. Pat. No. 4,697,140, filed Feb. 11, 1986, discloses a system wherein a switching circuit is responsive to a predetermined level of an input signal externally applied to a reset terminal for supplying a testing clock signal.
U.S. Pat. No. 4,583,179, filed Dec. 29, 1982, discloses a circuit wherein during an inspection period of an internal node to determine the condition of a fuse element a high voltage is supplied via an external input/output pin.